Sungmin Yun

Computer Architecture · Systems for AI

I am a Senior Deep Learning Performance Architect at NVIDIA, focusing on AI acceleration, performance analysis, and optimization. My work aims to maximize the performance and efficiency of AI systems through hardware–software co-design.

My experience spans accelerator design, hardware profiling, performance modeling, and kernel programming for modern AI architectures, including MoE, MLA, RAG, and diffusion. My research has focused on efficient LLM serving, Multi-LoRA inference, and RAG pipelines. I also developed LLMSimulator, an open-source end-to-end LLM performance simulator.

Previously, I was a postdoctoral researcher at Seoul National University (SNU). I received my Ph.D. in Artificial Intelligence from SNU, under the supervision of Prof. Jung Ho Ahn in the SCALE Lab. I received my B.S. in Integrated Information Technology from Yonsei University in 2020.

Publications

Education

Ph.D. in Artificial Intelligence
Seoul National University
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B.S. in Integrated Information Technology
Yonsei University
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Experience

Senior Deep Learning Performance Architect
NVIDIA
Deep learning application performance analysis.
– Present
Postdoctoral Researcher
Seoul National University
Led research on LLM serving systems, Multi-LoRA inference, and RAG pipeline acceleration.
–
Samsung Electronics Internship
Designed and implemented an HBM-PIM GEMV controller in RTL and developed the architecture behind Duplex (MICRO 2024).
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Awards

Best Ph.D. Dissertation Award
Seoul National University
Best of CAL Award
29th IEEE International Symposium on High-Performance Computer Architecture

Invited Presentations

Samsung AI Forum
Poster presentation
Best of CAL session at IEEE International Symposium on High-Performance Computer Architecture
Oral presentation

Academic Service

Program Committee

  • ISCA 2026 — Lightweight Program Committee Member

Journal Review

  • IEEE Transactions on Computers
  • IEEE Transactions on Circuits and Systems for Artificial Intelligence
  • IEEE Computer Architecture Letters
  • Future Generation Computer Systems
  • Journal of Supercomputing

Patents

Heterogeneous Computing Memory Device and Artificial Intelligence Computing System Including the Same
US · KR (10-2025-0050877)
Memory Device Capable of Dynamically Switching Between Error Correction Code and Error Detection Code in On-Die Error Correction Code
Memory Module and Computing System Including the Same
Memory Controller and Operation Method Thereof
Method and Apparatus for Memory Device Including Processing-in-Memory (PIM)
US (19/446,242) · KR (10-2025-0026131)
Memory System and Operating Method Thereof